Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
EDN

Verisity upgrades Verilog linting tool

SAN MATEO, Calif. — Verisity Design Inc. has released a new version of its SureLint Verilog linting tool that supports user-defined checks, better Finite State Machine and race condition checks, and ...
EDN

Innologic offers hierarchical Verilog simulator

SAN JOSE, Calif. — InnoLogic Systems Inc. is calling its ESP-BV the first commercial hierarchical Verilog simulator, a binary simulator that uses the company's “hierarchical compression” technology.
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...